1. Field of the Invention
The present invention relates to validation of integrated circuit designs.
2. State of the Art
As integrated circuit designs become increasingly complex, design validation and testing become increasingly important and increasingly difficult. Pre-silicon design validation may be distinguished from post-silicon testing. Design validation is both necessary and highly advantageous. Without some level of design validation, first-generation silicon parts may often be bug-ridden to an extent that renders post-silicon testing very difficult. Furthermore, xe2x80x9cdesign turnsxe2x80x9dxe2x80x94the cycle of redesign and fabricationxe2x80x94are costly and time consuming. Ideally, design validation would be sufficiently advanced as to eliminate further design turns.
Design validation has been largely based on software simulation. Software simulations, however, run in excess of six orders of magnitude slower than the real hardware being simulated. Current submicron process technology is capable of cost effectively implementing several million gates on a single die. To perform thorough validation of a design of 1M or more gates would typically require running the hardware in a validation laboratory for several months. To attempt to duplicate two months of hardware validation with software simulation would take hundreds of millenniaxe2x80x94clearly too long for the typical product cycle! Furthermore, software models are always abstractions of the real hardware such that there remains ambiguity as to the software model""s actual performance/function. Hence, as technology moves into the deep submicron region with its attendant complexity level, the conventional software simulation approach to integrated circuit design and validation is becoming obsolete.
The present invention, generally speaking, provides for validation of custom IC designs using standard ICs. Highly complex integrated circuits, instead of being designed at the gates and flops level, are typically designed using standardized cell libraries that allow for widespread, systematic design reuse. Such libraries may include Functional System Blocks, or FSBs (sometimes referred to as ASIC cores), and Application Specific Standard Parts (ASSPs). ASSPs are designs that are or were once realized as stand-alone parts, but that may also be embedded into larger designs (xe2x80x9cembedded ASSPsxe2x80x9d). Instead of using a conventional software model, validation is performed using a hardware model of a custom integrated circuit. The hardware model may be a breadboard system that may be decomposed into three levels of functionality: ASSPs, FSBs and xe2x80x9cglue logicxe2x80x9d In an exemplary embodiment, ASSPs are typically 500K gates or more and may be realized as separate ICs. FSBs are typically 50K gates or less. A collection of commonly used FSBs are therefore provided on a single integrated circuit (FSBIC) in such a way that by applying a predetermined control signal to the FSBIC, it will behave as a selected one of the FSBs. In an exemplary embodiment, the hardware model uses as many FSBICs as required to map to the FSBs in the custom IC design. Logic on the custom IC that is not part of an ASSP or an FSB may be regarded as glue logic. In an exemplary embodiment, a hardware emulator (e.g., a programmable logic IC) is used to model the glue logic. The resulting hardware model runs within one or two orders of magnitude of the speed of the custom IC design, allowing considerably more validation to be performed. The difference in speed between the hardware model and the specified design speed results largely from interconnect delays. In addition to running one nearly at design speed, the hardware model removes the doubt and ambiguity encountered in software simulation, since the least ambiguous specification for a function is a physical implementation of that function.